A conventional memory device based on magnetic random access memory (MRAM) cells is shown schematically in FIG. 1. The memory device 10 typically includes an array of word lines WL and bit lines BL that intersects to form an array. A MRAM cell 1 is coupled at each intersection of the word lines WL and bit lines BL. Each MRAM cell 1 comprises a magnetic tunnel junction 2, represented by a resistance, electrically coupled at one end to a select CMOS transistor 3. The magnetic tunnel junction 2 is typically formed to form an insulating layer in-between a reference layer and a storage layer (these element are not shown in FIG. 1). The word lines WL connect the MRAM cells 1 along a row via the gate of their respective transistors 3, while the bit lines BL connect the MRAM cells 1 along a column via the other end of their respective magnetic tunnel junction 2.
One of the MRAM cells 1, located at a corresponding intersection of one of the bit and word lines BL, WL, can be selected by providing the corresponding bit and word lines with a predetermined bias voltage value. In the example of FIG. 1, a selection circuitry 4 allows for selecting the bit and word lines BL, WL being supplied with the bias voltage.
During a so-called thermally assisted switching (TAS) writing operation of the selected MRAM cell 1, data is written by applying a single heating current pulse Iheat through the magnetic tunnel junction 2 in order to heat it above a predetermined high threshold temperature, while a magnetic field or a spin polarized current is applied to switch the magnetization of the storage layer. The MRAM cell 1 is then cooled down by switching off the heating current pulse Iheat, thereby freezing the magnetization of the storage layer in the written direction.
The data is then read by measuring the resistance magnetic tunnel junction, or magnetoresistance, by applying a sense voltage across the magnetic tunnel junction, at ambient temperature, or by passing a sense current through the magnetic tunnel junction and reading the resultant voltage.
One of the major drawbacks of this writing procedure is the necessary heating current Iheat to raise the temperature of the storage layer above its threshold temperature. Indeed, during the writing operation, the heating current is controlled by the bias voltage applied to both word and bit lines WL, BL. The magnitude of the heating current Iheat required to heat the magnetic tunnel junction 2 above the predetermined high threshold temperature imposes a constraint on the conductivity of the select transistor 3, depending on the size of the magnetic tunnel junction 2 in series with the transistor 3. For example, in order to reach a threshold temperature of 150° C. in the magnetic tunnel junction 2 having a surface area of 3.14·10−2 μm2, the heating current Iheat must have a value of about 200 μA, when using a low size select transistor (for example of 0.13 μm). Here, the heating current Iheat is given by Equation 1:
                                          I            heat                    =                      A            *                                          Pd                RA                                                    ,                            (                  Equation          ⁢                                          ⁢          1                )            
where A is the surface area of the magnetic tunnel junction 2, Pd the current power density in Watts cm−2, and RA the resistance-area product of the magnetic tunnel junction (insulating layer) in Ωcm2.
Since the size of the MRAM cell 1 is generally decreased due to increasing level of integration and scale down, the gate length and the oxide film thickness of the select transistor 3 are reduced. Therefore, a low memory array voltage, or core voltage, is used to power-up the MRAM cell 1, such as to reduce the power consumption and to improve the reliability of the select transistor 3. Indeed, using a high core voltage would produce a high channel electric field, possibly reaching a voltage-resistant limit of the select transistor oxide film, thus degrading the reliability of the select transistor 3.
It is therefore difficult to generate a value of the heating current that is high enough in most MRAM cells 1 by using the low core voltage. For example, in the case the core voltage has a value of 1.2 volts, and a voltage of 1.2 volts is applied to the world line WL and the bit line BL, the resulting heating current Iheat flowing through the magnetic tunnel junction 2 has a value of 130 μA. This is insufficient to reach the high threshold temperature of 150° C., and the cell 1 cannot be written.
Patent application WO2008109768 discloses a system, circuit and method for controlling a word line voltage at a word line transistor in spin transfer torque MRAM). A first voltage can be supplied to the word line transistor for write operations. A second voltage, which is less than the first voltage, can be supplied to the word line transistor during read operations. The risk of invalid write during the read operation is minimized.
Patent application EP2109111 discloses a TAS-MRAM cell comprising a magnetic tunnel junction a select transistor and a current line electrically connected to the junction, wherein the current line has a first function for passing a first portion of current for heating the junction, and a second function for passing a second portion of current in order to vary the resistance of the TAS-MRAM cell.